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| Disclaimer ATP Electronics Inc. shall not be liable for any errors or omissions that may appear in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth herein.ATP may make changes to specifications and product descriptions at any time, without notice. The information in this paper is furnished for informational use only so ATP assumes no responsibility or liability for any errors or inaccuracies that may appear in this document.All parts of the ATP documentation are protected by copyright law and all rights are reserved. This documentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior consent, in writing, from ATP Electronics, Inc.The information set forth in this document is considered to be "Proprietary" and "Confidential" property owned by ATP. |
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AF2GSDI|AF2DSDI-OEM|AF2GSDI-ZAEXM |
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1.0 Introduction ATP Industrial Grade SD cards are designed for demanding industrial applications, such as handheld computing, military/aerospace, automotive, marine navigation, embedded systems, communication equipment or networking, medical equipment, and automation, where mission-critical data requires the highest level of reliability, durability, and data integrity. 1.1 Main Features ⚫ Compatible with SD Specifications Version 2.00 ⚫ Support SD mode, SPI mode ⚫ High reliability, operating at -40 oC to 85 oC ⚫ SLC (Single-Level-Cell) NAND Flash ⚫ Water proof, Dust proof and ESD Resistant ⚫ SIP (System-In-Package) process ⚫ Resistance to Shock and Vibration ⚫ Enhanced endurance by Advanced Dynamic/Static Wear Leveling algorithm ⚫ Read Disturb Protector -AutoRefresh technology to ensure data integrity especially in frequent read operations ⚫ Enhanced power cycling support ⚫ Support BCH ECC up to 40bits/1KByte ⚫ Supports CPRM ⚫ Form factor: 32 x 24 x 2.1mm ⚫ RoHS compliant ⚫ CE & FCC certification ⚫ Controlled BOM ⚫ Customized service: adjustable CID registers, firmware & setting and label by projects |
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Note 1: Endurance for flash cards can be predicted based on the usage conditions applied to the device, the internal NAND flash cycles, the write amplification factor, and the wear leveling efficiency of the flash devices. Above TBW is for reference only. Please contact ATP for TBW in real applications. 1 TeraBytes = 1000 GigaBytes (Disk storage) Note 2: MTBF highly depends on testing method. All ATP products are tested with Bellcore Method II(Combines Method I predictions with laboratory data). |
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Note 1: Data retention refers to the ability of a memory bit to retain its data state over a period of time after the data is written in NAND Flash regardless of whether the part is powered on or powered off. A data retention failure is when there is at least 1 bit of data that cannot be read or is read incorrectly. Note 2: NAND Flash suppliers refer to JEDEC JESD47 & JESD22 for Data Retention testing. |
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Note 1: Tested by CrystalDiskMark 5.0.2 with 100MB file size. Note 2:The performance may vary depending on the configuration, firmware, setting, application and test environment |
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| The program / erase cycle of each sector/page/block is finite. Writing constantly on the same spot will cause the flash to wear out quickly. Furthermore, bit errors are not proportioned to P/E cycles; sudden death may occur when the block is close to its P/E cycle limit. Then unrecoverable bit errors will cause fatal data loss (especially for system data or FAT). Global wear leveling algorithm evenly distributes the P/E cycles of each block to minimize the possibility of one block exceeding its max P/E cycles before the rest. In return, the life expectancy of memory storage device is prolonged and the chance/occurrence of unrecoverable bit errors could be reduced.2.9 AutoRefresh Technology –Data Integrity ProtectionOver time the error bits accumulate to the threshold in the flash memory cell and eventually become uncorrectable despite using the ECC engine. In the traditional handling method, the data is moved to a different location in the flash memory; despite the corrupted data is beyond repaired before the transition. The situation is worse in frequent read applications, such as navigation systems or OS boot-up devices. The map or operation system is preloaded into the storage media and there may be one time write and following by read operation only. Read disturbance is the result of electrical interference from multiple read operations in surrounding pages. After NAND flash accumulates 100,000 read cycles, uncorrectable ECC errors may occur in the affected pages which results in data failure in the same block. To prevent data corruption, ATP memory product monitors the error bit levels in each read operation; when it reaches the preset threshold value, AutoRefresh is activated by programming the data into another block before the data is corrupted. After the re-programming operation is completed, the controller reads the data and compares the data/parity to ensure data integrity. Owing to different user experiences, please contact ATP for AutoRefresh in real applications.2.10 ATP PowerProtector –Power Cycling Protection The unstable power conditions of outdoor applications such as transportation, telecommunications/networking and embedded systems run the risk of data loss and drive corruption during a sudden power failure. A standalone hardware design is the ideal configuration for power backup, ensuring a sufficient amount of reserve power during any power abnormalities and minimizing the consequent host re-designs for adding new features. During a sudden power failure, the abnormality is discovered by a power loss detection circuit and activates the power protection mechanism. The device then draws power from power protection reservoir, where the reserve power is stored. The reserve power gives enough time for the flash device to conclude the last writing command without losing any data.4.0 S.M.A.R.T. Function 4.1 S.M.A.R.T. Feature Self-monitoring analysis and reporting technology (S.M.A.R.T.) is used to protect the user from unscheduled downtime. By monitoring and storing critical performance and calibration parameters, S.M.A.R.T. feature set devices attempt to predict the likelihood of near-term degradation or fault condition. Informing the host system of a negative reliability condition allows the host system to warn the user of the impending risk of a data loss and advise the user of appropriate action. 4.2 S.M.A.R.T. Feature Register Values In order to select a subcommand the host must write the subcommand code to the device's Features Register before issuing the S.M.A.R.T. function set command. The subcommands are listed below. |
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